Kavli Affiliate: Richard Foster
| First 5 Authors: Peter Orel, Abigail Y. Pan, Sven Herrmann, Tanmoy Chattopadhyay, Glenn Morris
| Summary:
The Advanced X-ray Imaging Satellite (AXIS) is a NASA probe class mission
concept designed to deliver arcsecond resolution with an effective area ten
times that of Chandra (at launch). The AXIS focal plane features an MIT Lincoln
Laboratory (MIT-LL) X-ray charge-coupled device (CCD) detector working in
conjunction with an application specific integrated circuit (ASIC), denoted the
Multi-Channel Readout Chip (MCRC). While this readout ASIC targets the AXIS
mission, it is applicable to a range of potential X-ray missions with
comparable readout requirements. Designed by the X-ray astronomy and
Observational Cosmology (XOC) group at Stanford University, the MCRC ASIC
prototype (MCRC-V1.0) uses a 350 nm technology node and provides 8 channels of
high speed, low noise, low power consumption readout electronics. Each channel
implements a current source to bias the detector output driver, a preamplifier
to provide gain, and an output buffer to interface directly to an
analog-to-digital (ADC) converter. The MCRC-V1 ASIC exhibits comparable
performance to our best discrete electronics implementations, but with ten
times less power consumption and a fraction of the footprint area. In a total
ionizing dose (TID) test, the chip demonstrated a radiation hardness equal or
greater to 25 krad, confirming the suitability of the process technology and
layout techniques used in its design. The next iteration of the ASIC (MCRC-V2)
will expand the channel count and extend the interfaces to external circuits,
advancing its readiness as a readout-on-a-chip solution for next generation
X-ray CCD-like detectors. This paper summarizes our most recent
characterization efforts, including the TID radiation campaign and results from
the first operation of the MCRC ASIC in combination with a representative
MIT-LL CCD.
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