Kavli Affiliate: Zheng Zhu
| First 5 Authors: Yihao Zhang, Sai Li, Albert Lee, Zheng Zhu, Lang Zeng
| Summary:
Physics-inspired computing paradigms, such as Ising machines, are emerging as
promising hardware alternatives to traditional von Neumann architectures for
tackling computationally intensive combinatorial optimization problems (COPs).
While quantum, optical, and electronic devices have garnered significant
attention for their potential in realizing Ising machines, their translation
into practical systems for industry-relevant applications remains challenging,
with each approach facing specific limitations in power consumption and speed.
To address this challenge, we report the first chip-level spintronic Ising
machine using voltage-controlled magnetoresistive random access memory. The
core of our design leverages magnetic tunnel junctions (MTJs) driven by the
voltage-controlled magnetic anisotropy effect to realize the probabilistic
update of Ising spins through a new mechanism. It enables a latency below 1 ns
and an energy consumption under 40 fJ per spin update, achieving a 1000-times
improvement over previous current-driven MTJ-based implementations. We map two
real-world COPs in electronic design automation-global routing and layer
assignment-onto the Ising model and demonstrate high-quality results with an
energy efficiency of 25000 solutions per second per watt. This outperforms
state-of-the-art quantum and graphics processing units by six and seven orders
of magnitude, respectively. These results establish voltage-controlled
spintronics as a compelling route towards next-generation physics-inspired
machine intelligence, offering a paradigm for ultra-low-power, high-speed, and
scalable computation.
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