Kavli Affiliate: Oskar Painter
| First 5 Authors: Harald Putterman, Kyungjoo Noh, Connor T. Hann, Gregory S. MacCabe, Shahriar Aghaeimeibodi
| Summary:
In order to solve problems of practical importance, quantum computers will
likely need to incorporate quantum error correction, where a logical qubit is
redundantly encoded in many noisy physical qubits. The large physical-qubit
overhead typically associated with error correction motivates the search for
more hardware-efficient approaches. Here, using a microfabricated
superconducting quantum circuit, we realize a logical qubit memory formed from
the concatenation of encoded bosonic cat qubits with an outer repetition code
of distance $d=5$. The bosonic cat qubits are passively protected against bit
flips using a stabilizing circuit. Cat-qubit phase-flip errors are corrected by
the repetition code which uses ancilla transmons for syndrome measurement. We
realize a noise-biased CX gate which ensures bit-flip error suppression is
maintained during error correction. We study the performance and scaling of the
logical qubit memory, finding that the phase-flip correcting repetition code
operates below threshold, with logical phase-flip error decreasing with code
distance from $d=3$ to $d=5$. Concurrently, the logical bit-flip error is
suppressed with increasing cat-qubit mean photon number. The minimum measured
logical error per cycle is on average $1.75(2)%$ for the distance-3 code
sections, and $1.65(3)%$ for the longer distance-5 code, demonstrating the
effectiveness of bit-flip error suppression throughout the error correction
cycle. These results, where the intrinsic error suppression of the bosonic
encodings allows us to use a hardware-efficient outer error correcting code,
indicate that concatenated bosonic codes are a compelling paradigm for reaching
fault-tolerant quantum computation.
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