Kavli Affiliate: Eric Oberla
| First 5 Authors: Jinseo Park, Evan Angelico, Andrew Arzac, Davide Braga, Ahan Datta
| Summary:
1 ps timing resolution is the entry point to signature based searches relying
on secondary/tertiary vertices and particle identification. We describe a
preliminary design for PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in
the TSMC 65 nm process targetting 1 ps resolution at 20 mW power per channel.
Each channel consists of four fast and one slow switched capacitor arrays
(SCA), allowing ps time resolution combined with a long effective buffer. Each
fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow
SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for
each channel is triggered by a fast discriminator capable of multiple
triggering during the window of the slow SCA. To achieve a large dynamic range,
low leakage, and high bandwidth, the SCA sampling switches are implemented as
2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are
digitized by an external ADC at 10 bits or better. Specifications on
operational parameters include a 4 GHz analog bandwidth and a dead time of 20
microseconds, corresponding to a 50 kHz readout rate, determined by the choice
of the external ADC.
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