Kavli Affiliate: Marshall Bautz
| Summary:
The Advanced X-ray Imaging Satellite (AXIS) is a Probe-class mission concept designed to deliver arcsecond spatial resolution, high-sensitivity spectral imaging across the 0.3-10 keV band. The X-ray Astronomy and Observational Cosmology (XOC) Group at Stanford, in collaboration with the MIT Kavli Institute (MKI) and MIT Lincoln Laboratory (MIT-LL), is developing the AXIS X-ray camera, including both the detector and the front-end readout electronics required to meet the mission’s demanding performance goals. The telescope’s focal plane detector consists of four 1440×1440 pixel charge-coupled devices (CCDs) developed by MIT-LL, each featuring 16 parallel output channels. These outputs are amplified by a high-speed, low-power, low-noise application-specific integrated circuit (ASIC) – the Multi-Channel Readout Chip (MCRC) – developed at Stanford. Following amplification, the analog signals are digitized and processed to construct a pixel array, prior to event detection. Here, we present the field-programmable gate array (FPGA) architecture developed to enable high-speed, parallelized readout of these CCD channels. The FPGA samples 16 analog-to-digital converter (ADC) channels at 50 MHz, performs preprocessing of pixel data, which is then streamed via User Datagram Protocol (UDP) over a 1 Gb Ethernet link to the back-end system for event reconstruction. Our design demonstrates the goal readout performance for AXIS (20 frames per second) and provides a framework for future high-throughput X-ray observatories.
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