Kavli Affiliate: Jing Wang
| First 5 Authors: Jing Wang, Jinyang Guo, Chao Li, ,
| Summary:
FPGA accelerators designed for graph processing are gaining popularity.
Domain Specific Language (DSL) frameworks for graph processing can reduce the
programming complexity and development cost of algorithm design. However,
accelerator-specific development requires certain technical expertise and
significant effort to devise, implement, and validate the system. For most
algorithm designers, the expensive cost for hardware programming experience
makes FPGA accelerators either unavailable or uneconomic. Although
general-purpose High-Level Synthesis (HLS) tools help to map high-level
language to Hardware Description Languages (HDLs), the generated code is often
inefficient and lengthy compared with the highly-optimized graph accelerators.
One cannot make full use of an FPGA accelerator’s capacity with low development
cost.
To easily program graph algorithms while keeping performance degradation
acceptable, we propose a graph programming system named JGraph, which contains
two main parts: 1) a DSL for graph atomic operations with a graph library for
high-level abstractions including user-defined functions with parameters, 2) a
light-weight HLS translator to generate high-performance HDL code, cooperating
with a communication manager and a runtime scheduler. To the best of our
knowledge, our work is the first graph programming system with DSL and
translator on the FPGA platform. Our system can generate up to 300 MTEPS BFS
traversal within tens of seconds.
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