Kavli Affiliate: Huawei Zhang| First 5 Authors: Zhiteng Chao, Zhiteng Chao, , , | Summary:Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog. However, challenges remain in ensuring the quality of Verilog generation. Complex designs often fail in a single generation […]
Continue.. Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT