Kavli Affiliate: Jing Wang
| First 5 Authors: Wenkai Li, Wenkai Li, , ,
| Summary:
Accurate power prediction in VLSI design is crucial for effective power
optimization, especially as designs get transformed from gate-level netlist to
layout stages. However, traditional accurate power simulation requires
time-consuming back-end processing and simulation steps, which significantly
impede design optimization. To address this, we propose ATLAS, which can
predict the ultimate time-based layout power for any new design in the
gate-level netlist. To the best of our knowledge, ATLAS is the first work that
supports both time-based power simulation and general cross-design power
modeling. It achieves such general time-based power modeling by proposing a new
pre-training and fine-tuning paradigm customized for circuit power. Targeting
golden per-cycle layout power from commercial tools, our ATLAS achieves the
mean absolute percentage error (MAPE) of only 0.58%, 0.45%, and 5.12% for the
clock tree, register, and combinational power groups, respectively, without any
layout information. Overall, the MAPE for the total power of the entire design
is <1%, and the inference speed of a workload is significantly faster than the
standard flow of commercial tools.
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