Kavli Affiliate: Jing Wang
| First 5 Authors: Jing Wang, Jing Wang, , ,
| Summary:
High-level synthesis (HLS) accelerates hardware design by enabling the
automatic translation of high-level descriptions into efficient hardware
implementations. However, debugging HLS code is a challenging and
labor-intensive task, especially for novice circuit designers or software
engineers without sufficient hardware domain knowledge. The recent emergence of
Large Language Models (LLMs) is promising in automating the HLS debugging
process. Despite the great potential, three key challenges persist when
applying LLMs to HLS logic debugging: 1) High-quality circuit data for training
LLMs is scarce, posing a significant challenge. 2) Debugging logic bugs in
hardware is inherently more complex than identifying software bugs with
existing golden test cases. 3) The absence of reliable test cases requires
multi-tasking solutions, performing both bug identification and correction.
complicates the multi-tasking required for effective HLS debugging. In this
work, we propose a customized solution named HLSDebugger to address the
challenges. HLSDebugger first generates and releases a large labeled dataset
with 300K data samples, targeting HLS logic bugs. The HLSDebugger model adopts
an encoder-decoder structure, performing bug location identification, bug type
prediction, and bug correction with the same model. HLSDebugger significantly
outperforms advanced LLMs like GPT-4 in bug identification and by more than 3x
in bug correction. It makes a substantial advancement in the exploration of
automated debugging of HLS code.
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